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PRELIMINARY SPECIFICATION
PE9304
Rad Hard for Space Applications
Product Description
The PE9304 is a high-performance CMOS prescaler with a fixed divide ratio of 2. Its operating frequency range is 1GHz to 7GHz. The PE9304 operates on a nominal 3 V supply and draws only 13.5mA. It is packaged in a small 8-lead ceramic SOIC and is ideal for frequency scaling and clock generation solutions. The PE9304 is manufactured in Peregrine's patented Ultra-Thin Silicon (UTSi ) CMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS.
1- 7 GHz Low Power CMOS Divide-by-2 Prescaler
Features * Fixed divide ratio of 2 * Low-power operation: 13.5mA typical @ 3 V * Small package: 8-lead Ceramic SOIC * Guaranteed 100Krads(Si) Total Dose Performance * Superior Single Event Upset Immunity
Figure 1. Functional Schematic Diagram
Figure 2. Package Type
8 Lead Gullwing Glass Flatpack
.380 / .410 .210 / .250 .180 SQ Max .166 SQ TYP Pin 1
.050 TYP .150 TYP .015 TYP
Table 1. Electrical Specifications (ZS = ZL = 50 )
VDD = 3.0 V, -40 C TA 85 C, unless otherwise specified
Parameter
Supply Voltage Supply Current Input Frequency (Fin)
Conditions
Minimum
2.85
Typical
3.0 13.5
Maximum
3.15 18.0 7 +12 +12 +12
Units
V mA GHz dBm dBm dBm dBm
1 1GHz Fin < 2GHz +5 0 +5 0 -7 -12
Input Sensitivity (Pin)
2GHz Fin < 6GHz 6 GHz Fin 7GHz 1GHz Fin < 2GHz
Output Power (Pout)
2GHz Fin < 6GHz 6 GHz Fin 7GHz
PEREGRINE SEMICONDUCTOR CORP.
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Copyright Peregrine Semiconductor Corp. 2003
Page 1 of 6
PE9304
Preliminary Specification
Figure 3. Pin Configuration
VDD IN DEC GND 1 2 8 7 GND OUT NC GND
Electrostatic Discharge (ESD) Precautions When handling this UTSi device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 3. Latch-Up Avoidance Unlike conventional CMOS devices, UTSi CMOS devices are immune to latch-up.
Description
(R) (R)
PE9304
3 4 6 5
Table 2. Pin Descriptions
Pin No.
1 2 3 4
Pin Name
VDD IN DEC GND
Power supply pin. Bypassing is required (eg. 1000pF & 100pF). Input signal pin. Should be coupled with a capacitor (eg. 2.2pF). Decoupling Pin. This pin should have two capacitors in parallel (eg. 1000pf, 10nF) Ground pin. Ground pattern on the board should be as wide as possible to reduce ground impedance. Ground pin. No connection. This pin should be left open. Divided frequency output pin. This pin should be coupled with a capacitor (eg. 2.2pF). Ground Pin.
Device Functional Considerations The PE9304 divides a 1GHz - 7GHz input signal by a factor of two thereby producing an output frequency at half the input frequency. To work properly at higher frequencies, the input and output signals (pins 2 & 7) must be AC coupled via an external capacitor, as shown in the test circuit in Figure 7. The ground pattern on the board should be made as wide as possible to minimize ground impedance.
5 6 7
GND NC OUT
8
GND
Table 3. Absolute Maximum Ratings
Symbol
VDD Pin VIN TST TOP
Parameter/Conditions
Supply voltage Input Power Voltage on input Storage temperature range Operating temperature range ESD voltage (Human Body Model, MIL-STD 883 Method 3015.7)
Min
Max
3.3 +12
Units
V dBm V C C V
-0.3 -65 -40
VDD +0.3 150 85 500
VESD
ESD voltage (Machine Model, JEDEC, JESD22A114-B) ESD voltage (Charged Device Model, JEDEC, JESD22-C101)
50
V
1000
V
Copyright Peregrine Semiconductor Corp. 2003
File No. 70/0152~00A
| UTSi
CMOS RFIC SOLUTIONS
Page 2 of 6
PE9304
Preliminary Specification
Typical Performance Data: VDD = 3.0V Figure 4. Input Sensitivity Figure 5. Device Current
Specified Operating Window
Figure 6. Output Power
PEREGRINE SEMICONDUCTOR CORP. |
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Copyright Peregrine Semiconductor Corp. 2003
Page 3 of 6
PE9304
Preliminary Specification
Figure 7. Evaluation Board Schematic Diagram
J2-9
Figure 8. Evaluation Board Layout
C10 1000 pF
C2 100 pF
1
VDD
GND
8
2
IN
OUT
7
J1
2.2pF
C4 1000pF C6 10nF
C3 1000 pF
3
C1 1000 pF NC NC
6
J3
2.2pF
4
GND
GND
5
J4
J5
Evaluation Kit Operation The Ceramic SOIC Prescaler Evaluation Board was designed to help customers evaluate the PE9304 divide-by-2 prescaler. On this board, the device input (pin 2) is connected to the SMA connector J1 through a 50 transmission line. A series capacitor (C3) provides the necessary DC block for the device input. A value of 2.2pF was used for the evaluation board; other applications may require a different value. The device output (pin 7) is connected to SMA connector J3 through a 50 transmission line. A series capacitor (C1) provides the necessary DC block for the device output. This capacitor value must be chosen to have low impedance at the desired output frequency of the device. A value of 2.2pF was chosen for the evaluation board.
J2 provides DC power to the device via pin 1. Two decoupling capacitors (C2=1000pF, C10=100pF) are included on this trace. It is the responsibility of the customer to determine proper supply decoupling for their design application. The board is constructed using 4 layers. The top and bottom layers are comprised of Rogers low loss 4350 material having a core thickness of 0.010"; while the internal layers are comprised of FR-4. The overall board thickness is 0.062". Applications Support If you have a problem with your evaluation kit or if you have applications questions call (858) 455-0660 and ask for applications support. You may also contact us by fax or e-mail: Fax: (858) 455-0770 E-Mail: help@peregrine-semi.com
Copyright Peregrine Semiconductor Corp. 2003
File No. 70/0152~00A
| UTSi
CMOS RFIC SOLUTIONS
Page 4 of 6
PE9304
Preliminary Specification
Figure 9. Package Drawing
8 Lead Gullwing Glass Flatpack
.380 / .410
.210 / .250 Pin 1 .180 SQ MAX
.050 TYP .150 TYP
TOP VIEW
.015 TYP
SIDE VIEW
.070 MAX
Table 4. Ordering Information
Order Code
9304-01 9304-11 9304-00
Part Marking
PE9304 PE9304 PE9304-EK
Description
PE9304-08CFPG-1A Engineering Samples PE9304-08CFPG-1A Flight Units PE9304 Evaluation Kit
Package
Gullwing Glass Flatpack Gullwing Glass Flatpack Evaluation Kit
Shipping Method
20 / Tray 50 / Tray 1 / Box
PEREGRINE SEMICONDUCTOR CORP. |
http://www.peregrine-semi.com
Copyright Peregrine Semiconductor Corp. 2003
Page 5 of 6
PE9304
Preliminary Specification
Sales Offices
United States
Peregrine Semiconductor Corp.
6175 Nancy Ridge Drive San Diego, CA 92121 Tel 1-858-455-0660 Fax 1-858-455-0770
Japan
Peregrine Semiconductor K.K.
5A-5, 5F Imperial Tower 1-1-1 Uchisiawaicho, Chiyoda-ku, Tokyo, Japan 100-011 Tel. 011-81-3-3502-5211 Fax. 011-81-3-3502-5213
Europe
Peregrine Semiconductor Europe
Aix-En-Provence Office Parc Club du Golf, bat 9 13856 Aix-En-Provence Cedex 3 France Tel 33-0-4-4239-3360 Fax 33-0-4-4239-7227 For a list of representatives in your area, please refer to our Web site at: http://www.peregrine-semi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice.
The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. Peregrine products are protected under one or more of the following U.S. patents: 6,090,648; 6,057,555; 5,973,382; 5,973,363; 5,930,638; 5,920,233; 5,895,957; 5,883,396; 5,864,162; 5,863,823; 5,861,336; 5,663,570; 5,610,790; 5,600,169; 5,596,205; 5,572,040; 5,492,857; 5,416,043. Other patents are pending.
Preliminary Specification
The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a PCN (Product Change Notice).
Peregrine, the Peregrine logotype, Peregrine Semiconductor Corp., and UTSi are registered trademarks of Peregrine Semiconductor Corporation. Copyright (c) 2002 Peregrine Semiconductor Corp. All rights reserved.
Copyright Peregrine Semiconductor Corp. 2003 File No. 70/0152~00A
| UTSi
CMOS RFIC SOLUTIONS
Page 6 of 6

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